AMD’s Massive SP5 Socket That Will Power Future EPYC CPUs Has Been Pictured In All Its Glory
The latest pictures come from forum member of STH (ServerTheHome, 111alan. This is the first close-up and physical look of the AMD SP5 socket that we have gotten so far. As expected, AMD’s SP5 socket will feature 6096 LGA contact pads to support the future generation of EPYC CPUs such as Genoa (up to 96 cores) and Bergamo (up to 128 cores). The pictured socket is from a dual 2P platform which houses two SP5 sockets and a total of 24 DIMM slots (2 DIMMs per channel for a total of 12 channel memory support). The LGA 6096 socket will feature 6096 pins arranged in the LGA (Land Grid Array) format. This will be by far the biggest socket that AMD has ever designed with 2002 more pins than the existing LGA 4094 socket. We have already listed the size and dimensions of this socket above so let’s talk about its power ratings. It looks like the peak power of the LGA 6096 SP5 socket will be rated at up to 700W which will only last for 1ms, the peak power at 10ms is rated at 440W while the peak power with PCC is rated at 600W. If the cTDP is exceeded, then the EPYC chips featured on the SP5 socket will return to these limits within 30ms.
AMD EPYC Milan Zen 3 vs EPYC Genoa Zen 4 Size Comparisons:
The socket will support AMD’s EPYC Genoa and future generations of EPYC chips. Talking about Genoa CPUs themselves, the chips will pack a mammoth 96 cores and 192 threads. These will be based on AMD’s brand new Zen 4 core architecture which is expected to deliver some insane IPC uplifts while utilizing the TSMC 5nm process node. The physical chip is a gargantuan on its own with one of the largest CPU package ever as pictured below: Other than that, it is stated that AMD’s EPYC Genoa CPUs will feature 128 PCIe Gen 5.0 lanes of which 112 PCIe Gen 5 lanes will be available since the remaining 16 are reserved, 160 for a 2P (dual-socket) configuration. The SP5 platform will also feature DDR5-5200 memory support which is some insane improvement over the existing DDR4-3200 Mbps DIMMs. But that’s not all, it will also support up to 12 DDR5 memory channels and 2 DIMMs per channel which will allow up to 12 TB of system memory using 1 TB 3DS RDIMM modules. In addition to this, a leaked AMD slide also confirms future EPYC SOCs to feature higher DDR5 pin speeds of up to 6000-6400 Mbps. This could probably be referring to Turin or Bergamo as they are the ones that succeed Genoa. The main competitor of AMD’s EPYC Genoa lineup would be Intel’s Sapphire Rapids Xeon family which is expected to launch in 2022 too with PCIe Gen 5 and DDR5 memory support. The lineup was recently rumored to not get a volume ramp until 2023. Overall, AMD’s Genoa lineup seems to be in great form after this leak and could be a major disruption for the server segment if AMD plays its cards right till Genoa’s launch by 2022. News Source: HXL
